1. Field of the Invention
Embodiments of the present invention generally relate to a process for depositing a metal on a substrate.
2. Description of the Related Art
Active matrix liquid crystal displays have become the display technology of choice for numerous applications including computer monitors, television screens, camera displays, avionics displays, as well as numerous other applications. Active matrix liquid crystal displays generally comprise an array of picture elements called pixels. An electronic switch is associated with each pixel in the display to control the operation thereof. Various electronic switches such as, for example, thin film transistors and organic light emitting diodes (OLED), have been investigated to control pixel operation. Thin film transistors (TFT). in particular, offer a high degree of design flexibility and device performance. Thin film transistors are generally formed on large area substrates having a high degree of optical transparency such as glass.
FIG. 1 depicts a cross-sectional schematic view of a thin film transistor 1 having a bottom gate structure. The thin film transistor 1 includes a glass substrate 10 having an optional underlayer 20 formed thereon. A gate is formed on the underlayer 20. The gate comprises a gate metal layer 30 and a gate dielectric layer 40. The gate controls the movement of charge carriers in the transistor. The gate dielectric layer 40 electrically isolates the gate metal layer 30 from semiconductor layers 50 and 70 (70a, 70b), formed thereover, each of which may function to provide charge carriers to the transistor.
An interlayer dielectric/etch stop layer 60 is formed on semiconductor layer 50 to isolate source and drain aspects of semiconductor layer 70 and conductive layer 80. Source and drain structures comprise a source contact 80a disposed on source region 70a and drain contact 80b disposed on drain region 70b. Finally, a passivation layer 90 encapsulates the thin film transistor 1 to protect the transistor from environmental hazards such as moisture and oxygen.
The gate metal layer 30 generally comprises a conductive material, of which copper and copper alloys have become the metals of choice for TFT technology since copper has a lower resistivity than aluminum, (1.7 μΩ-cm for copper compared to 3.1 μΩ-cm for aluminum), a higher current carrying capacity and significantly higher electromigration resistance. These characteristics are important for supporting the current densities experienced at high levels of integration across large areas (i.e., glass substrates). Further, copper has a good thermal conductivity and is available in a highly pure state.
Conventionally, copper is deposited onto materials using physical vapor deposition (PVD) techniques. However, gate material layers deposited using PVD techniques generally tend to have higher resistivities than desired for device performance, which may affect the electrical performance of the transistors, including device reliability and premature failure.
Additionally, copper may be deposited on materials, such as dielectric materials, that vary by physical characteristics and the adhesion of copper to the dielectric materials can be problematic. Copper materials have also been observed to delaminate and flake from the surfaces of some underlying materials. In addition, copper may not deposit to particular surfaces since nucleation sites may not be available.
Other techniques to deposit copper, such as by chemical vapor deposition often result in blanket deposition of copper that must be removed to form selected features. Copper is also known as being difficult to etch from the surface of a substrate, and removal of copper may result in defect formation and damage to the underlying substrate. Additionally, copper is difficult to pattern and techniques, such as damascene or dual damascene formation, to form patterned copper features, have not been found or not considered suitable for forming TFTs.
Therefore, there is a need for a method of selectively depositing a metal material on a substrate.